Due to the limitations of the size, weight and power of micro-nano satellites, the field programmable gate array (FPGA) is required to provide high energy efficiency computing ability for the onboard sea-land segmentation of large filed remote sensing images. Under the premise of ensuring the segmentation accuracy, the key is to utilize the limited on-chip resources of FPGA to realize parallel computing for low computational complexity algorithms. Therefore, a multi-threshold hierarchical sea-land segmentation based on FPGA parallel computing is proposed in this article. The proposed method takes OTSU as the core method, and uses the sub-image classification based on multi-feature joint threshold to construct hierarchical sea-land segmentation. In this way, the influence of interference points in the sea are suppressed. In addition, a novel parallel iterative computing architecture is designed, which can improve the computing efficiency of OTSU, and achieve the balance adjustment of on-chip memory occupancy. Experimental results show that the overall precision of the method proposed can achieve more than 98% . Meanwhile, the processing time of the proposed method is only 0. 16 s for the 8 192×2 048 pixels remote sensing image. Compared with other FPGA-based methods, the processing time is reduced by 23. 81% at least.