With the development of deep learning technology and the increasing demand for image scene understanding, the application of semantic segmentation networks based on FPGA to provide low-latency and high-energy-efficiency edge-end intelligent services for all users has become a research hotspot. The computing and storage of the semantic segmentation network structure have the intensive feature. To address this issue, the construction of a customized FPGA-based computing structure is a key research issue. In view of this, this paper summarizes the basic principles of semantic segmentation networks and analyzes the characteristics of its internal calculation structure, then elaborates FPGA-based semantic segmentation network computing acceleration methods from two perspectives: model compression methods with hardware resource constraints and custom hardware architecture design. Furthermore, this paper focuses on a summary and analysis of typical methods of computing structure design and memory access optimization in hardware architecture design. Finally, this paper looks forward to the future development trend of FPGA-accelerated computing methods for semantic segmentation networks, in order to provide design references for researchers in semantic segmentation, edge computing, customized energy-efficient computing and other related fields.